This invention relates to device for and method of evaluating a semiconductor integrated circuit in which a transistor is arranged.
Recently, in promotion of a highly integrated, miniaturized semiconductor integrated circuit, it is hard to specify a fault point with only information outputted from the semiconductor integrated circuit as an electric signal. Hence, non-contact evaluating method and device become more important for evaluating inside the semiconductor integrated circuit. As non-contact evaluating devices of the semiconductor integrated circuit, there are an electron beam tester and an emission microscope.
The electron beam tester scans a semiconductor integrated circuit in a vacuum sample room with an electron beam to observe and evaluate a potential profile inside the semiconductor circuit by a secondary electron to be detected (reflection electron).
The emission microscope observes a weak radiation occurring in the semiconductor integrated circuit in order to detect and evaluate breakage inside the semiconductor integrated circuit and an undesired state in reliability, in cases where:
(1) an insultor is broken: PA0 (2) a forward bias is applied to a diffusion layer (p-n junction) or the diffusion layer is broken: PA0 (3) a hot carrier occurs in a transistor; and PA0 (4) a latch up occurs.
Such an emission microscope is produced by, for example, Hamamatsu Photonics K.K. as Hot Electron Analyzer, C3230.
Another emission microscope for evaluating a property of the semiconductor Integrated circuit is disclosed in Japanese Patent Application Laying Open Gazette No. 63-119541. In the emission microscope, potential profile or potential state inside the semiconductor integrated circuit is obtained by observing the photon emission of a transistor connected to, for example, HIGH level signal wiring.
Further, in Japanese Patent Application Laying Open Gazette No. 4-79345, a part of connection fault or insulation fault in the integrated circuit is rapidly specified in such a manner that an emission pattern occurring in a normal circuit when a given patterned voltage is applied is pre-memorized as a reference image and an image when the same patterned voltage is applied to a semiconductor integrated circuit to be analyzed is compared with the reference image utilizing a fact that connection and disconnection in the semiconductor integrated circuit can be detected upon the presence of the radiation of the transistor.
The above conventional techniques, however, have respective problems.
In the electron beam tester, the sample room should be vacuous, which causes the tester to be in a large scale. As a result a skilled operation is required and it is difficult to maintain the tester and to prepare the measurement.
In the emission microscope, the radiation caused by the hot carrier mentioned in (3) is also observed in a semiconductor integrated circuit with acceptable quality. Thus it is difficult to judge acceptance or rejection by the radiation. Further, only the observation of the radiation merely informs whether the potential state is at HIGH or at LOW. Thus, information which can be fed back to a design, such as a delay time of the transistor and a switching time of the input gate signal is hard to obtain, such as in the electron beam tester.
On the other hand, when the optical radiation caused by the hot carrier is observed by the emission microscope utilizing analyzing or testing methods disclosed in the respective disclosures, there is no problem such as in the electron beam tester. However, only the potential profile in the integrated circuit can be obtained by the method in the former disclosure, and only the fault point owing to disconnection and insulation fault can be specified by the analyzing method in the latter disclosure. In consequence, information on a delay time of the transistor and on a switching time of an input gate signal cannot be obtained by either methods.